FIG. 1 shows a system of the prior art with a processor 12, interface logic 15, and a memory unit 18. The processor 12 addresses the memory unit 18 using memory address multiplexing where each memory address comprises a row address and a column address. The addressing is "multiplexed" in the sense that the memory unit 18 accepts the row address and the column address sequentially rather than simultaneously.
A cycle begins with the processor 12 placing an address on the address bus 24, and control signals on the control bus 21. If the interface logic 15 determines that the cycle is a memory cycle, the state machine 59 selects the row portion of the address applied to the multiplexer 33 and communicates this row address over port 38 to the memory device address port 17. The state machine 59 asserts the RAS control signal 45 to strobe the row address into the memory device 18. The row address is then removed from the address port 17, and the column portion of the address is selected and presented to the address port 17 over bus 36. The state machine 59 then asserts the CAS control signal 42, thereby strobing the column address into the memory device 18.
Depending on whether the memory cycle is a read or write operation, either the output enable (OE) signal 48 or the write enable (WE) signal 51 is appropriately asserted by the state machine 59. During a write operation, data is moved from the data bus 27 to the memory unit 18. During a read operation, data is moved from the memory unit 18 to the data bus 27. Optional transceivers 29 and 30 can be used to buffer information being transferred to and from the memory unit 18. Transceiver 29 buffers data being transferred on the bus 28 between the data bus 27 and the memory unit 18. Transceiver 30 buffers the address being transferred on the bus 36 from the interface logic 15 to the memory unit 18.
Thus, in the system of FIG. 1, the interface logic 15 accepts the full address from the address lines 24 and sequentially communicates the corresponding multiplexed address portions over the port 38 and bus 36. The interface logic 15 of FIG. 1 is relatively complicated because it must accept the full address on one set of inputs and deliver the multiplexed address to the memory unit 18 over port 38. This complexity adds to the pin requirements or pin count and physical size of the interface logic 15. Accordingly, there exists a need to reduce the pin count (i.e., cost) of the interface logic 15 without any sacrifice in performance, but while also retaining full compatibility with the processor 12, the memory unit 18, and their associated protocol.